module regfile(
    input clk,
    input reset,
    input en,
    input [4:0] raddr1,
    input [4:0] raddr2,
    input [4:0] waddr,
    input [63:0] wdata,
    
    output [63:0] rdata1,
    output [63:0] rdata2,
    output wire [63:0] regs_o[0:31]
);

    reg [63:0] regfile[0:31];
    
    assign rdata1 = raddr1 == 5'b00000 ? 64'd0 : regfile[raddr1];
    assign rdata2 = raddr2 == 5'b00000 ? 64'd0 : regfile[raddr2];

    always@(posedge clk) begin
        if(reset) begin
            integer i;
            for(i = 0;i < 32;i = i + 1) begin
                regfile[i] <= 64'd0;
            end
        end else if(en && (waddr != 5'b00000)) begin
            regfile[waddr] <= wdata;
        end
    end

    genvar i;
	generate
		for (i = 0; i < 32; i = i + 1) begin
			assign regs_o[i] = regfile[i];
		end
	endgenerate

endmodule
